It finds one application in electronic circuits that have to produce clocks phase-shifted with great accuracy from a reference clock of very high frequency, typically greater than 1 GHz.
Thus it finds one application in phase-locked loop (PLL) systems or delay-locked loop (DLL) systems, in which it is necessary to convert a time offset into a proportional voltage with great accuracy.
The architecture of a prior art phase-locked loop system has been described with reference to FIG. 1. Such a phase-locked loop system generally includes:
a phase comparator, PC;
a time-voltage converter, TVC, equipped with a charge pump, CP, and a low-pass filter, PB; and
a voltage-controlled delay line, CVDL.
The clock signals Clkout of the voltage-controlled delay line CVDL are clock signals of the same frequency as the clock signal Clkref but mutually phase-shifted by a duration that has to be controlled with great accuracy.
The phase comparator PC compares the reference clock signal Clkref and the last clock signal Clkdly from the delay line. The two clock signals Clkref and Clkdly must be in phase when the loop is locked.
In practice, the phase comparator PC delivers two logic signals Up and Dwn that are the image of the phase shift between the two clock signals Clkref and Clkdly to be perfectly synchronized. When the two clocks are not yet synchronized, the logic signals Up and Dwn have different durations.
It is this difference of duration that is to be converted into a proportional voltage, which is then integrated over time, in order to correct the error by means of a feedback loop.
Accordingly, the difference of duration between the signals Up and Dwn is converted into an integrated proportional voltage Vup-Vdwn that controls the delay line CVDL.
The static phase error in the phase-locked loop system from FIG. 1 has been described with reference to FIG. 2.
The static phase error ΔTspe is measured in locked mode and corresponds to a constant offset between the input clock signals of the phase comparator PC. It is the sum of all the mismatch errors present in the phase comparator PC and the time-voltage conversion block TVC.
The static phase error acts directly on the offset of the phase-shifted clock signals and constitutes the principal source of error in a phase-locked loop system.
Prior art phase-locked loop systems include particular architectures called “symmetrical structure” architectures, that is to say architectures based on symmetry in time-voltage conversion for the Up and Dwn channels for all operations carried out at high frequency.
Such architectures are known to reduce the static phase error structurally.
For example, one known symmetrical architecture is based on a differential charge pump, like that described in the document “A 500 MHz MP/DLL Clock Generator for 5 Gb/s Backplane Transceiver in 0.25 μm CMOS”, ISCC 2003.
Another symmetrical time-voltage conversion structure is described in the patent application filed this day by the Applicant and entitled “Symmetrical time-voltage conversion circuit”. In case it is of any benefit, the description of that application forms an integral part of the present invention.
The symmetrical architecture based on such a differential charge pump CP has been described with reference to FIGS. 3 and 4. In practice, the charge pump CP includes four control switches S1 to S4, S1 and S2 having for control input the signals Up and Dwn, respectively, and S3 and S4 having for control input the complements Upb and Ddwnb of the signals Up and Dwn, respectively.
The circuit further includes eight current flow transistors S5 to S12. The flow transistors S5 and S6 are means that regulate the flow of a current as a function of the bias voltage Vb1. The flow transistors S7 and S8 are controlled by a bias voltage Vb2. The flow transistors S9 and S10 are controlled by a bias voltage Vb3. The flow transistors S11 and S12 are controlled by a bias voltage Vb4.
Transistors S13 and S14 are controlled by a common mode feedback block CMFB. The block CMFB controls the common output mode, that is to say the mean level of the voltages Vdiff+ and Vdiff−.
When the signals Up and Dwn are opposed, the currents Iup and Idwn flow in the loop filter FB and are integrated to produce a differential voltage (Vdiff+−Vdiff−). That differential voltage is converted into a unipolar signal Vint by a converter CDU to control a delay line CVDL.
The structure of this differential architecture is called symmetrical in that the currents Iup and Idwn are generated by means of transistors of identical type and size. Similarly, the transistors S5 to S12 for the signals Up and Dwn are identical.
Three blocks have been added to compensate the static phase error.
An additional phase comparator CPA is used to detect the static phase error by comparing the clocks Clkref and Clkdly.
The Up and Dwn indications from the phase detector CPA are integrated in a digital counter CN.
A digital-analog converter CNA with current output is used to adjust the currents Iup and Idwn and to compensate the mismatch.
The compensation technique proposed in this differential charge pump architecture reduces the static phase error of the principal blocks but adds a source of error because of the mismatches present in the additional phase comparator CPA.